M. Togo, R. Asra, P. Balasubramaniam, X. Zhang, H. Yu, S. Yamaguchi, E. Geiss, H. Yang, B. Cohen, H. Lo, O. Hu, H. Lazar, O. Kwon, D. Burnett, J. Versaggi, E. Banghart, M. K. Hassan, E. Bazizi, L. Pantisano, J. G. Lee, S. Samavedam, D. K. Sohn
{"title":"用于超低电压工作的多功能高性能finfet","authors":"M. Togo, R. Asra, P. Balasubramaniam, X. Zhang, H. Yu, S. Yamaguchi, E. Geiss, H. Yang, B. Cohen, H. Lo, O. Hu, H. Lazar, O. Kwon, D. Burnett, J. Versaggi, E. Banghart, M. K. Hassan, E. Bazizi, L. Pantisano, J. G. Lee, S. Samavedam, D. K. Sohn","doi":"10.1109/VLSIT.2018.8510641","DOIUrl":null,"url":null,"abstract":"A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm2 SRAM array.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"81-82"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Multiple Workfunction High Performance FinFETs for Ultra-low Voltage Operation\",\"authors\":\"M. Togo, R. Asra, P. Balasubramaniam, X. Zhang, H. Yu, S. Yamaguchi, E. Geiss, H. Yang, B. Cohen, H. Lo, O. Hu, H. Lazar, O. Kwon, D. Burnett, J. Versaggi, E. Banghart, M. K. Hassan, E. Bazizi, L. Pantisano, J. G. Lee, S. Samavedam, D. K. Sohn\",\"doi\":\"10.1109/VLSIT.2018.8510641\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm2 SRAM array.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"1 1\",\"pages\":\"81-82\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510641\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510641","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiple Workfunction High Performance FinFETs for Ultra-low Voltage Operation
A multiple workfunction (multi-WF) integration technology was developed for ultra-low voltage operation in high performance FinFETs. It is essential to solve three key issues in the multi-WF process, a) short channel effect (SCE) degradation due to removing halo implants b) gate resistance increase due to multi-WF stack, and c) gate dielectric reliability degradation due to additional patterning. In this study, we resolve these issues through the combination of junction engineering and workfunction metal (WFM) boolean engineering in long channel (LC) and short channel (SC) devices for SCE, WFM stack optimization for gate resistance, and HK interface optimization for reliability. In logic devices, 15/13% N/PFET DC and 14% AC performance were improved without SCE or reliability degradation. In SRAM devices, 43% Vt mismatch (Vtmm) improvement resulted in record Vmin yield down to 0.4V on 128Mb 0.064μm2 SRAM array.
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