在低于0.18 /spl mu/m技术下高速缓存设计的数据感知方案的缩放

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852898

K. Zhang, K. Hose, V. De, B. Senyk

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引用次数: 49

摘要

从技术尺度的角度对片上缓存设计中的小信号差分数据感知进行了评价。随着硅制程技术超过0.18 /spl mu/m，传统方案越来越难以保持延迟缩放趋势和高面积效率。提出了一种具有大信号传感的替代设计方案，并证明在深亚微米区域是一种可行的设计方案。

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The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies

Small signal differential data sensing for on-chip cache design is evaluated from the perspective of technology scaling. Maintaining the delay scaling trend and high area efficiency is getting more difficult with the conventional scheme as Si process technology moves beyond 0.18 /spl mu/m. An alternative design scheme with large signal sensing is proposed and proven to be a viable design alternative in the deep sub-micron regime.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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