一种用于在3位/单元闪存中实现5mb /s程序速率的选择性验证方案

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852880

H. Kurata, N. Kobayashi, S. Saeki, T. Kawahara

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引用次数: 5

摘要

由于音频和视频存储的应用，对闪存中高密度和高速编程的需求不断增长。多层技术是提高内存密度的最有效方法，但它需要精确控制内存单元的Vth，而不会降低编程性能。为了实现这一点，我们开发了一种基于同步多级编程的高速编程的选择性验证方案。一种具有非对称单元操作和双银行操作的选择性验证方案使得在3位/单元的闪存中实现5mb /s的编程吞吐量。

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A selective verify scheme for achieving a 5-MB/s program rate in 3-bit/cell flash memories

The demand for high density and high-speed programming in flash memories has grown because of audio- and video- storage applications. A multilevel technique is the most effective approach to improving memory density, but it requires precise control of a memory cell's Vth that doesn't degrade programming performance. To enable this, we have developed a selective verify scheme for high-speed programming based on simultaneous multilevel programming. A selective verify scheme with asymmetrical cell operation and two-bank operation makes 5-MB/s programming throughput in 3-bit/cell flash memories attainable.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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