Q-scheduler:一种温度和能量感知的深度q -学习技术,用于调度实时多处理器嵌入式系统中的任务

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mahsa Mohammadi, Hakem Beitollahi
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引用次数: 2

摘要

在处理器温度限制下降低能耗已成为当前实时多处理器系统(mpsoc)面临的一个紧迫问题。处理器温度过高会影响MPSoC的功耗和可靠性。低能耗是实时嵌入式系统的必要条件,因为它们大多数是便携式设备。处理器上高效的任务映射对降低处理器的能耗和热分布有重要的影响。最近提出了几种最先进的技术来解决这个问题。本文提出了一种基于深度q学习技术的新技术Q-scheduler,用于实时MPSoC的处理器间任务调度。数千个模拟任务离线训练Q-scheduler,以减少处理器温度限制下的系统功耗。经过训练的Q-scheduler在实时MPSoC中在线调度实际任务,同时也定期在线接受培训。Q-scheduler用一个进程同时调度系统中的多个任务;这种能力的有效性是显著的,特别是在谐波实时系统中。实验结果表明,与之前的先进技术相比,Q-scheduler平均可将处理器的能耗和温度分别降低15%和10%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Q-scheduler: A temperature and energy-aware deep Q-learning technique to schedule tasks in real-time multiprocessor embedded systems

Q-scheduler: A temperature and energy-aware deep Q-learning technique to schedule tasks in real-time multiprocessor embedded systems

Reducing energy consumption under processors' temperature constraints has recently become a pressing issue in real-time multiprocessor systems on chips (MPSoCs). The high temperature of processors affects the power and reliability of the MPSoC. Low energy consumption is necessary for real-time embedded systems, as most of them are portable devices. Efficient task mapping on processors has a significant impact on reducing energy consumption and the thermal profile of processors. Several state-of-the-art techniques have recently been proposed for this issue. This paper proposes Q-scheduler, a novel technique based on the deep Q-learning technology, to dispatch tasks between processors in a real-time MPSoC. Thousands of simulated tasks train Q-scheduler offline to reduce the system's power consumption under temperature constraints of processors. The trained Q-scheduler dispatches real tasks in a real-time MPSoC online while also being trained regularly online. Q-scheduler dispatches multiple tasks in the system simultaneously with a single process; the effectiveness of this ability is significant, especially in a harmonic real-time system. Experimental results illustrate that Q-scheduler reduces energy consumption and temperature of processors on average by 15% and 10%, respectively, compared to previous state-of-the-art techniques.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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