减少代码大小的标量替换中的移位寄存器初始化

Q4 Engineering
Kenshu Seto
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引用次数: 2

摘要

标量替换是一种有效的技术,可以提高由具有密集数组访问的C程序的高级综合(high-level synthesis, HLS)生成的RTL代码的性能。在标量替换中,从数组访问的数据被存储到移位寄存器中,随后对相同数据的数组访问被替换为对移位寄存器的访问,而不是对数组的访问。也就是说,标量替换用移位寄存器访问替换数组访问。由于C程序中的数组通常映射到端口数量有限的ram,因此使用标量替换减少数组访问会导致内存访问减少,从而提高生成的RTL代码的性能。在实际的C程序中,有时移位寄存器必须使用多个数组访问来有条件地初始化,这增加了主循环中数组访问的次数。为了减少主循环中的条件数组访问,先前的标量替换方法提出了一种称为循环剥离的循环变换。环路剥离会导致代码大小的显著增加,从而对合成硬件的性能或电路面积产生负面影响。在本文中,我们提出了一种新的方法来初始化移位寄存器而不产生环路剥离。所提出的方法是在标量替换之前对输入C程序进行预处理。实验结果表明,与之前的方法相比,所提出的方法减少了合成硬件的执行周期。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Shift Register Initialization in Scalar Replacement for Reducing Code Size
: Scalar replacement is an e ff ective technique to improve the performance of the RTL code generated by high-level synthesis (HLS) from C programs with intensive array accesses. In scalar replacement, data accessed from arrays are stored into shift registers, and later array accesses on the same data are replaced with the accesses to the shift registers instead of the arrays. Namely, scalar replacement replaces array accesses with shift register accesses. Since arrays in C programs are usually mapped to RAMs with limited numbers of ports, reducing array accesses with scalar replacement leads to the memory access reduction, which in turn improves the performance of the resulting RTL code. In real-life C programs, sometimes, shift registers must be initialized conditionally using multiple array accesses, which increases the number of array accesses in main loops. To reduce the conditional array access in the main loops, the previous scalar replacement method proposed the use of a loop transformation called loop peeling. Loop peeling brings significant increase in code size, leading to the negative impacts on performance or circuit area of the synthesized hardware. In this paper, we propose a new method to initialize shift registers without loop peeling. The proposed method works as a preprocessing of the input C program prior to scalar replacement. With experimental results, we demonstrate the proposed method reduces the numbers of execution cycles of the synthesized hardware compared to the previous method.
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来源期刊
IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology Engineering-Electrical and Electronic Engineering
CiteScore
1.20
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