采用先进基板工艺开发新型有机中间体细线2.1 D封装

Wei-chung Chen, C. Lee, H. Kuo, Min-Hua Chung, Chaung-Chi Wang, Shang-Kun Huang, Yen-Sen Liao, Chen-Chao Wang, D. Tarng
{"title":"采用先进基板工艺开发新型有机中间体细线2.1 D封装","authors":"Wei-chung Chen, C. Lee, H. Kuo, Min-Hua Chung, Chaung-Chi Wang, Shang-Kun Huang, Yen-Sen Liao, Chen-Chao Wang, D. Tarng","doi":"10.1109/ICSJ.2018.8602655","DOIUrl":null,"url":null,"abstract":"Development of 2.1D package with organic interposer in panel size based on the high resolution dry film photoresist and the ultra-thin electro-less copper seed layer will be reported in this paper. The aim of 2.1D technology is focus on the reducing of production cost and increase I/O counts simultaneously. Compare to the wafer level lithography process, substrate-based process leads to the benefit in cost reduction and risk elusion form chip first process. The high resolution photolithography semi-additive processes (SAP) can achieve 3 µm copper line width and 25 µm laser drilled vias in panel size (510*408mm). On the other hand, the sputtered metal seed layer can be replaced by electro-less copper plating seed layer (approximately 0.1 µm). When it comes to cost, dry film photoresist and electro-less copper seed layer processes can significantly save the equipment and material cost compared to the wafer patterning process. These high density interconnection lines, micro-bump pads and vias are integrated and demonstrated on an organic film in the thickness of 25 µm. Micro-bump pads designed for the copper pillar bond are with a 25 µm diameter and a 40 µm pitch. Flip chip bond alignment is verified by the x-ray examination. The embedded trace substrate (ETS) by using plating nickel thin layer for etching resistance, copper trace with 3 µm width and spacing embedded in the organic film can be formed with very good flatness performance. Moreover, this designed 2.1D organic interposer substrate has passed the MSL3 (Moisture Soaking Level 3) standard and the TCT (Thermal Cycling Test) reliability test with 1000 cycles. In terms of electrical property study, kinds of dielectric materials and high resolution photoresists are employed in this study. The electrical measurement including DC resistance and S-parameter is performed to tell apart the different performance of dielectric and photoresist materials, and the result show agreement with the formed appearance of copper traces.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"12 1","pages":"601-606"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Development of Novel Fine Line 2.1 D Package with Organic Interposer Using Advanced Substrate-Based Process\",\"authors\":\"Wei-chung Chen, C. Lee, H. Kuo, Min-Hua Chung, Chaung-Chi Wang, Shang-Kun Huang, Yen-Sen Liao, Chen-Chao Wang, D. Tarng\",\"doi\":\"10.1109/ICSJ.2018.8602655\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Development of 2.1D package with organic interposer in panel size based on the high resolution dry film photoresist and the ultra-thin electro-less copper seed layer will be reported in this paper. The aim of 2.1D technology is focus on the reducing of production cost and increase I/O counts simultaneously. Compare to the wafer level lithography process, substrate-based process leads to the benefit in cost reduction and risk elusion form chip first process. The high resolution photolithography semi-additive processes (SAP) can achieve 3 µm copper line width and 25 µm laser drilled vias in panel size (510*408mm). On the other hand, the sputtered metal seed layer can be replaced by electro-less copper plating seed layer (approximately 0.1 µm). When it comes to cost, dry film photoresist and electro-less copper seed layer processes can significantly save the equipment and material cost compared to the wafer patterning process. These high density interconnection lines, micro-bump pads and vias are integrated and demonstrated on an organic film in the thickness of 25 µm. Micro-bump pads designed for the copper pillar bond are with a 25 µm diameter and a 40 µm pitch. Flip chip bond alignment is verified by the x-ray examination. The embedded trace substrate (ETS) by using plating nickel thin layer for etching resistance, copper trace with 3 µm width and spacing embedded in the organic film can be formed with very good flatness performance. Moreover, this designed 2.1D organic interposer substrate has passed the MSL3 (Moisture Soaking Level 3) standard and the TCT (Thermal Cycling Test) reliability test with 1000 cycles. In terms of electrical property study, kinds of dielectric materials and high resolution photoresists are employed in this study. The electrical measurement including DC resistance and S-parameter is performed to tell apart the different performance of dielectric and photoresist materials, and the result show agreement with the formed appearance of copper traces.\",\"PeriodicalId\":6555,\"journal\":{\"name\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"12 1\",\"pages\":\"601-606\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSJ.2018.8602655\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSJ.2018.8602655","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

本文将介绍基于高分辨率干膜光刻胶和超薄化学镀铜种层的2.1D面板尺寸有机中间体封装。2.1D技术的目标是在降低生产成本的同时增加I/O数量。与晶圆级光刻工艺相比,基于基板的工艺在降低成本和规避风险方面优于芯片优先工艺。高分辨率光刻半增材工艺(SAP)可以在面板尺寸(510*408mm)上实现3µm铜线宽度和25µm激光钻孔。另一方面,溅射金属种层可以用化学镀铜种层代替(约0.1µm)。在成本方面,干膜光刻胶和化学铜籽层工艺与晶圆图片化工艺相比,可以显着节省设备和材料成本。这些高密度互连线,微凸垫和过孔被集成并展示在厚度为25微米的有机薄膜上。为铜柱粘结设计的微碰撞垫直径为25微米,间距为40微米。倒装芯片键对是通过x射线检查验证的。采用镀镍抗蚀刻的薄层嵌入微量衬底(ETS),在有机薄膜中嵌入宽度为3µm且间距为3µm的铜微量,具有很好的平整度性能。此外,所设计的2.1D有机中间层衬底通过了MSL3 (Moisture seetting Level 3)标准和TCT (Thermal cycle Test) 1000次循环可靠性测试。在电性能研究方面,采用了多种介电材料和高分辨率光刻胶。通过直流电阻和s参数等电学测量来区分介电材料和光刻胶材料的不同性能,结果与形成的铜迹相吻合。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Development of Novel Fine Line 2.1 D Package with Organic Interposer Using Advanced Substrate-Based Process
Development of 2.1D package with organic interposer in panel size based on the high resolution dry film photoresist and the ultra-thin electro-less copper seed layer will be reported in this paper. The aim of 2.1D technology is focus on the reducing of production cost and increase I/O counts simultaneously. Compare to the wafer level lithography process, substrate-based process leads to the benefit in cost reduction and risk elusion form chip first process. The high resolution photolithography semi-additive processes (SAP) can achieve 3 µm copper line width and 25 µm laser drilled vias in panel size (510*408mm). On the other hand, the sputtered metal seed layer can be replaced by electro-less copper plating seed layer (approximately 0.1 µm). When it comes to cost, dry film photoresist and electro-less copper seed layer processes can significantly save the equipment and material cost compared to the wafer patterning process. These high density interconnection lines, micro-bump pads and vias are integrated and demonstrated on an organic film in the thickness of 25 µm. Micro-bump pads designed for the copper pillar bond are with a 25 µm diameter and a 40 µm pitch. Flip chip bond alignment is verified by the x-ray examination. The embedded trace substrate (ETS) by using plating nickel thin layer for etching resistance, copper trace with 3 µm width and spacing embedded in the organic film can be formed with very good flatness performance. Moreover, this designed 2.1D organic interposer substrate has passed the MSL3 (Moisture Soaking Level 3) standard and the TCT (Thermal Cycling Test) reliability test with 1000 cycles. In terms of electrical property study, kinds of dielectric materials and high resolution photoresists are employed in this study. The electrical measurement including DC resistance and S-parameter is performed to tell apart the different performance of dielectric and photoresist materials, and the result show agreement with the formed appearance of copper traces.
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