FPGA implementation of Saliency based secured watermarking framework

In this paper authors proposed a secured Digital Biometric based watermarking algorithm and its hardware realization by means of Field Programmable Gate Array (FPGA). The scheme focuses on the Graph Based Visual Saliency (GBVS) technique. Biometric watermarking has been introduced for validity and ultimate security of a digital media. Biometric information which is basically fingerprint is being hidden in a cover image in an efficient way such that the quality of the original information is not corrupted. The result of imperceptibility is promising; moreover several attacks were made to prove the robustness of this technique. The hardware implementation of this algorithm is provided to validate this scheme.