Design of Efficient Dynamic Scheduling of RISC Processor Instructions

The state of art Tomasulo's Algorithm is implemented in a quite different manner. It has multiple data bus lines for out-of-order execution to eliminate data hazards and even to minimize control and structural hazards at compile-time, that connects the reservation station to the execution units. And reservation station controls the instruction execution, is a decentralized scheduler a feature of CPU which allows register renaming to eliminate WAR/WAW hazards. But for this project with the use of multiple data bus lines will have multiple reservation stations to eliminate the structural and control hazards. Cache coherence protocol is about maintaining consistency among multiple local caches so that storing/fetching data will be easier in various cases for multiprocessor systems. So, this modified Tomasulo's algorithm is implemented in conjunction with caches for writing this result and to attain coherency.