栅极偏置对NMOS器件ESD特性的影响

2011 International Symposium on Advanced Packaging Materials (APM) Pub Date : 2011-12-19 DOI:10.1109/ISAPM.2011.6105756

Yujuan He, Y. En, Hongwei Luo, Qingzhong Xiao

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引用次数: 1

摘要

MOSFET在使用过程中在氧化区产生的氧化物捕获电荷会引起ESD特性的改变。因此栅极强迫给定偏置来模拟氧化物捕获电荷。本文采用TLP测试方法研究了不同栅极偏置下NMOSFET的ESD参数。结果表明，阈值电压Vt1和二次击穿电流It2随栅极电压的升高先升高后降低，但维持电压Vsp基本不变。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Effect of gate bias on ESD characteristics in NMOS device

Oxide trapped charges which were produced in oxide area of MOSFET in the process of using can cause ESD characteristic changed. So the gate forced given bias to Simulate oxide trapped charges. In this paper, TLP test method was used to study the ESD parameters of NMOSFET with various gate biases. It was indicated that the threshold voltage Vt1 and secondary breakdown current It2 first increased and then decreased with the gate voltage increasing, but the maintained Voltage Vsp essentially unchanged.

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2011 International Symposium on Advanced Packaging Materials (APM)

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