基于概率密度函数的大型集成电路可靠性评估

N. C. Laurenciu, S. Cotofana
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引用次数: 1

摘要

对于当前先进的技术节点,需要在设计时进行准确而快速的可靠性分析,以实现不同电路架构之间的比较,从而实现对可靠性敏感的设计和综合过程。为此,我们提出了一个可靠性评估框架,该框架能够更准确地估计电路可靠性,并可应用于大规模电路设置,通过:(i)考虑到电路拓扑(隐含其再收敛扇出),输入向量,环境条件和故障场景,(ii)采用一系列概率,即概率密度函数(PDF),而不是迄今为止的单一概率值,以量化电路可靠性,(iii)采用变分推理,在给定其主要输入PDF的情况下推导电路主要输出PDF,(iv)采用传统的变分推理方法来利用概率模型传入逻辑电路的特性,以提高收敛速度,从而适用于大规模电路设置。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Probability density function based reliability evaluation of large-scale ICs
For the current advanced technology nodes, an accurate, yet fast reliability analysis is needed at design time, to enable the comparison between different circuit architectures, and thus a reliability-aware design and synthesis process. To this end we propose a reliability assessment framework that is able to estimate more accurately the circuit reliability and which can be applied to large-scale circuit settings, by: (i) taking into account the circuit topology (and implicitly its reconvergent fanouts), the input vectors, the environmental conditions and fault scenarios, (ii) employing a range of probabilities, i.e., a Probability Density Function (PDF), instead of hitherto single probability value, in order to quantify the circuit reliability, (iii) employing variational inference, to derive the circuit primary output PDFs, given its primary inputs PDFs, and (iv) adapting the traditional variational inference approach to exploit the peculiarities of the probabilistic model afferent to logic circuits, for convergence speed improvements and thus applicability in large scale circuits settings.
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