L. Shan, Daniel Freidman, Craig Kennedy, Warren Persak, K. Lau
{"title":"下一代PCIe电气I/O向后兼容连接器","authors":"L. Shan, Daniel Freidman, Craig Kennedy, Warren Persak, K. Lau","doi":"10.1109/ECTC.2018.00270","DOIUrl":null,"url":null,"abstract":"A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"128 1","pages":"1798-1804"},"PeriodicalIF":0.0000,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Backward Compatible Connectors for Next Generation PCIe Electrical I/O\",\"authors\":\"L. Shan, Daniel Freidman, Craig Kennedy, Warren Persak, K. Lau\",\"doi\":\"10.1109/ECTC.2018.00270\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.\",\"PeriodicalId\":6555,\"journal\":{\"name\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"128 1\",\"pages\":\"1798-1804\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2018.00270\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2018.00270","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Backward Compatible Connectors for Next Generation PCIe Electrical I/O
A backward compatible PCIe connector targeting 25-32Gb/s per-channel data rates was jointly developed under a collaboration between IBM Research and Amphenol Corporation. To demonstrate the improvement on loss/reflection/crosstalk, an evaluation board with both original and new PCIe connector footprints was designed, fabricated, and tested. 3D full-wave simulations were performed and correlated with measurement results. Optimal pad and ground configurations were used to update PCIe channel budget/specifications and provide design recommendations for potential PCIe Gen5 channels.