Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

Aim: The aim of this work is to construct an innovative pMos logic based comparator and analyze the power consumption and compare with the nMos logic based comparator. Material and methods: The comparator is designed by using the Tanner tool version 16.01 for simulation and verification. By varying the length of a transistors in a circuit the power values were obtained. This experiment is performed for 20 different values of length. Results: The power consumption of a pMos logic based comparator was minimum (2.2656 ± 0.37933), followed by the nMos logic based comparator (7.7494 ± 0.41603), the less power consumption seen in pMos logic based comparator significance (.955). Conclusion: The consumption of power by the constructed pMos logic based comparator appears to have less power consumption than the nMos logic based comparator.