Stratix®10:14nm FPGA,提供1GHz

M. Hutton
{"title":"Stratix®10:14nm FPGA,提供1GHz","authors":"M. Hutton","doi":"10.1109/HOTCHIPS.2015.7477458","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"142 1","pages":"1-24"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Stratix® 10: 14nm FPGA delivering 1GHz\",\"authors\":\"M. Hutton\",\"doi\":\"10.1109/HOTCHIPS.2015.7477458\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"142 1\",\"pages\":\"1-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477458\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477458","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

本文由作者在会议上的演讲幻灯片组成。总结要点包括:3D集成不仅仅是集成,它是-去风险、工艺匹配、衍生品增殖和滴答;设备布局和配置得到升级-软件控制允许安全性和功能的设备;SoC集成是主流——处理器成本是芯片、相干加速器的一个小子集;流水线可以在FPGA架构中实现优化——有效地使用导线,而不是强迫它们更快——当你可以将设计提高到更高效的地方时,更快==更低的功耗;工艺仍然给我们带来了功耗优势- 14nm三栅极降低了功耗,实现了更高性能的电路设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Stratix® 10: 14nm FPGA delivering 1GHz
This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信