{"title":"Stratix®10:14nm FPGA,提供1GHz","authors":"M. Hutton","doi":"10.1109/HOTCHIPS.2015.7477458","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"142 1","pages":"1-24"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Stratix® 10: 14nm FPGA delivering 1GHz\",\"authors\":\"M. Hutton\",\"doi\":\"10.1109/HOTCHIPS.2015.7477458\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.\",\"PeriodicalId\":6666,\"journal\":{\"name\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"volume\":\"142 1\",\"pages\":\"1-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Hot Chips 27 Symposium (HCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HOTCHIPS.2015.7477458\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Hot Chips 27 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2015.7477458","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This article consists of a collection of slides from the author's conference presentation. Summary points include: 3D integration isn't just integration, it is - De-risking, process matching, derivative proliferation and tick/tock; Device floorplanning and configuration get an upgrade - Software control allows for security and feature-up of devices; SoC integration is mainstream - Processor cost is a small subset of the die, coherent-accelerators; Pipelining unlocks optimizations in FPGA architecture - Using wires efficiently, not brute-forcing them faster - Faster == lower power when you can get designs to a more efficient place; Process is still giving us power benefits - 14nm Tri-Gate reduces power, enabling higher performance circuit-design.