{"title":"基于陷阱动力学的三维动力学蒙特卡罗模拟用于UTBB mosfet可靠性评估","authors":"Wangyong Chen, Linlin Cai, Xiaoyan Liu, G. Du","doi":"10.1109/SISPAD.2019.8870505","DOIUrl":null,"url":null,"abstract":"Trap dynamics based 3D Kinetic Monte Carlo (KMC) simulator is developed to offer physical insights into the electrical characteristics degradation and quantitative reliability evaluation for advanced MOSFETs. The physics-based 3D KMC simulation enables to reproduce the evolution of stress-induced charge distribution in the multi-layer dielectrics and identify the trap impact on the degradation of device performance. Simulation results of UTBB FDSOI MOSFETs reveal that assumption of the uniform charge distribution in the dielectrics induced by stress underestimates the statistical degradation and variability. It also shows that the higher intrinsic trap density of back-gate oxide leads to the larger degradation and its variability, especially for the increased back-gate bias case.","PeriodicalId":6755,"journal":{"name":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Trap Dynamics based 3D Kinetic Monte Carlo Simulation for Reliability Evaluation of UTBB MOSFETs\",\"authors\":\"Wangyong Chen, Linlin Cai, Xiaoyan Liu, G. Du\",\"doi\":\"10.1109/SISPAD.2019.8870505\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Trap dynamics based 3D Kinetic Monte Carlo (KMC) simulator is developed to offer physical insights into the electrical characteristics degradation and quantitative reliability evaluation for advanced MOSFETs. The physics-based 3D KMC simulation enables to reproduce the evolution of stress-induced charge distribution in the multi-layer dielectrics and identify the trap impact on the degradation of device performance. Simulation results of UTBB FDSOI MOSFETs reveal that assumption of the uniform charge distribution in the dielectrics induced by stress underestimates the statistical degradation and variability. It also shows that the higher intrinsic trap density of back-gate oxide leads to the larger degradation and its variability, especially for the increased back-gate bias case.\",\"PeriodicalId\":6755,\"journal\":{\"name\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"volume\":\"45 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.2019.8870505\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.2019.8870505","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Trap Dynamics based 3D Kinetic Monte Carlo Simulation for Reliability Evaluation of UTBB MOSFETs
Trap dynamics based 3D Kinetic Monte Carlo (KMC) simulator is developed to offer physical insights into the electrical characteristics degradation and quantitative reliability evaluation for advanced MOSFETs. The physics-based 3D KMC simulation enables to reproduce the evolution of stress-induced charge distribution in the multi-layer dielectrics and identify the trap impact on the degradation of device performance. Simulation results of UTBB FDSOI MOSFETs reveal that assumption of the uniform charge distribution in the dielectrics induced by stress underestimates the statistical degradation and variability. It also shows that the higher intrinsic trap density of back-gate oxide leads to the larger degradation and its variability, especially for the increased back-gate bias case.