Design and simulation of LV PLL with ALF D-charge pump in 90 nm CMOS technology

With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of PLL. The time has come to break one of the famous Silicon Valley golden rules which states "Higher the clock frequency, Greater the power consumption". Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. At lower supply voltage, it is challenging to optimize each block of PLL for Low Voltage operations. A Low voltage High Frequency ALF Charge Pump PLL is proposed. It employs a differential Charge pump with an active loop filter to compensate current mismatch and reduces reference spurs. A Voltage Controlled Oscillator is designed with body bias technique providing wide capture range and low power consumption. A D Flip Flop PFD is designed with TSPC dynamic logic to achieve zero or minimum dead zone and is able to detect large phase and frequency difference.