B. Sirbu, Y. Eichhammer, H. Oppermann, T. Tekin, J. Kraft, V. Sidorov, X. Yin, J. Bauwelinck, C. Neumeyr, Francisco Soares
{"title":"用于数据中心Tb/s光互连的3D硅光子中间体,具有双面组装有源元件和集成光电通过SOI硅孔","authors":"B. Sirbu, Y. Eichhammer, H. Oppermann, T. Tekin, J. Kraft, V. Sidorov, X. Yin, J. Bauwelinck, C. Neumeyr, Francisco Soares","doi":"10.1109/ECTC.2019.00165","DOIUrl":null,"url":null,"abstract":"In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55µm wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"78 1","pages":"1052-1059"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical Through Silicon Via on SOI\",\"authors\":\"B. Sirbu, Y. Eichhammer, H. Oppermann, T. Tekin, J. Kraft, V. Sidorov, X. Yin, J. Bauwelinck, C. Neumeyr, Francisco Soares\",\"doi\":\"10.1109/ECTC.2019.00165\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55µm wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.\",\"PeriodicalId\":6726,\"journal\":{\"name\":\"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)\",\"volume\":\"78 1\",\"pages\":\"1052-1059\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2019.00165\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00165","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D Silicon Photonics Interposer for Tb/s Optical Interconnects in Data Centers with Double-Side Assembled Active Components and Integrated Optical and Electrical Through Silicon Via on SOI
In this paper, we present the concept, fabrication, process and packaging of a 3D Si photonics interposer. This Si photonics interposer merges passive photonic and electronic functionalities within a single chip. The interposer is populated with active optical and electronic add-ons, which are flip-chip bonded to the interposer using thermo-compression bonding. The interposer itself is then flip-chip bonded to a glass and Si carrier for further testing purposes. This integration concept enables a high connection density (Gb/s/mm²) by assembling 40Gb/s per channel opto-electrical components on both sides of the interposer. Communication between components on both sides of the interposer is enabled by optical and electrical TSVs with a 3dB bandwidth >28GHz. A single mode photonic layer, designed for 1.55µm wavelength is integrated within the interposer to be used for routing and switching of the optical signals. Main fabrication and packaging steps are described here, together with some demonstrator evaluation results.