H. Rhee, Ilryong Kim, Jaehun Jeong, Nakjin Son, Heebum Hong, Sungil Cho, Yongsoon Park, Dongwoo Kim, Yunki Choi, Jeonghoon Ahn, S. Kang, K. Yeo, Jungtae Kim, Euncheol Lee, J. Youn, J. Yoon
{"title":"8LPP逻辑平台技术，用于高成本效益的大批量生产","authors":"H. Rhee, Ilryong Kim, Jaehun Jeong, Nakjin Son, Heebum Hong, Sungil Cho, Yongsoon Park, Dongwoo Kim, Yunki Choi, Jeonghoon Ahn, S. Kang, K. Yeo, Jungtae Kim, Euncheol Lee, J. Youn, J. Yoon","doi":"10.1109/VLSIT.2018.8510673","DOIUrl":null,"url":null,"abstract":"8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44nm EUV-less multi-patterning BEOL process, resulting in 7% power reduction and ~15% area scaling compared with the previous 10LPP. The cost-effective high volume manufacturing is achieved with the minimum additional critical layers and the comparable process steps over the current high volume 10nm production.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"21 1","pages":"217-218"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"8LPP Logic Platform Technology for Cost-Effective High Volume Manufacturing\",\"authors\":\"H. Rhee, Ilryong Kim, Jaehun Jeong, Nakjin Son, Heebum Hong, Sungil Cho, Yongsoon Park, Dongwoo Kim, Yunki Choi, Jeonghoon Ahn, S. Kang, K. Yeo, Jungtae Kim, Euncheol Lee, J. Youn, J. Yoon\",\"doi\":\"10.1109/VLSIT.2018.8510673\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44nm EUV-less multi-patterning BEOL process, resulting in 7% power reduction and ~15% area scaling compared with the previous 10LPP. The cost-effective high volume manufacturing is achieved with the minimum additional critical layers and the comparable process steps over the current high volume 10nm production.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"21 1\",\"pages\":\"217-218\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510673\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510673","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
8LPP Logic Platform Technology for Cost-Effective High Volume Manufacturing
8LPP logic platform technology supports mobile and high-performance and lower power application especially for mobile, artificial intelligence (AI), and cryptocurrency devices. 8LPP is employing the evolutionary generation of bulk FinFET FEOL and 44nm EUV-less multi-patterning BEOL process, resulting in 7% power reduction and ~15% area scaling compared with the previous 10LPP. The cost-effective high volume manufacturing is achieved with the minimum additional critical layers and the comparable process steps over the current high volume 10nm production.
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