D. Kwon, Y. Liao, Yen-Kai Lin, J. Duarte, K. Chatterjee, A. Tan, A. Yadav, C. Hu, Z. Krivokapic, S. Salahuddin
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We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.
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