Experimental reliability study of cumulative damage models on state-of-the-art semiconductor technologies for step-stress tests and mission profile stresses

Cumulative damage models are essential for reliability analysis, whether it is for the development of time-saving step-stress or ramp-stress life tests or for the qualification of products against mission-profile-based lifetime requirements. Although many cumulative damage models have been proposed in the literature, the discussion on them is rarely based on empirical data. In order to contribute to the experimental investigation of those models, three well-established models are tested for their validity. Thus, the cumulative exposure, the tampered random variable, and the tampered failure rate models are introduced in such a way that is supportive of multilevel step-stress accelerated life testing. Subsequently, experimental reliability data of semiconductor devices are used to verify or disprove the predicted failure behavior of all three models. For this purpose, university MOS-capacitors and the 22FDX® technology from GLOBALFOUNDRIES are tested. The chosen failure mechanism is the voltage and temperature accelerated time-dependent dielectric breakdown.