B. Peethala, D. Sil, B. Briggs, D. Rath, N. Lanzillo, K. Matam, H. Shobha, K. Choi, T. Spooner, D. Canaperi, B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang, K. Ryan
{"title":"7nm以上全对准通孔集成的金属湿凹槽挑战和解决方案","authors":"B. Peethala, D. Sil, B. Briggs, D. Rath, N. Lanzillo, K. Matam, H. Shobha, K. Choi, T. Spooner, D. Canaperi, B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang, K. Ryan","doi":"10.1109/IITC51362.2021.9537484","DOIUrl":null,"url":null,"abstract":"The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":"110 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2021-07-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration\",\"authors\":\"B. Peethala, D. Sil, B. Briggs, D. Rath, N. Lanzillo, K. Matam, H. Shobha, K. Choi, T. Spooner, D. Canaperi, B. Haran, M. Packiam, D. Janes, J. Casey, L. Chang, K. Ryan\",\"doi\":\"10.1109/IITC51362.2021.9537484\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.\",\"PeriodicalId\":6823,\"journal\":{\"name\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"volume\":\"110 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-07-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC51362.2021.9537484\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC51362.2021.9537484","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Metal Wet Recess Challenges and Solutions for beyond 7nm Fully Aligned Via Integration
The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractors and their contributions are not well understood. One of the key challenges in FAV integration is the need to create of topography which can be either achieved by recessing the metal lines or by selective insulator deposition. Wet recess process has been promising for enabling downstream integration learning of conformal cap deposition, ultra low-k gap-fill, and via landing on recessed area. In this paper wet recess challenges for topography creation and key process improvements that improve the resistance distribution are discussed.