{"title":"基于尾数指数表示的实时音调映射算法的硬件实现","authors":"Ulian Shahnovich, Alain Horé, O. Yadid-Pecht","doi":"10.1109/ISCAS.2016.7539021","DOIUrl":null,"url":null,"abstract":"This paper presents a hardware implementation of a mantissa/exponent-based tone mapping algorithm for wide dynamic range (WDR) images. The algorithm performs tone mapping by using a global compression model for the pixel intensities combined with a local contrast enhancement model. The pixel intensities of the WDR images used in this paper are represented in a mantissa/exponent format produced by an innovative WDR imager which takes advantage of a multi-reset technique during the capture process. The algorithm has been implemented on FPGA and designed to be very small, fast, power-efficient and has the potential to be directly integrated into the same chip as the imager. Experimental results performed by using different images show that our implementation is reliable and efficient.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"35 1","pages":"2210-2213"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Hardware implementation of a real-time tone mapping algorithm based on a mantissa-exponent representation\",\"authors\":\"Ulian Shahnovich, Alain Horé, O. Yadid-Pecht\",\"doi\":\"10.1109/ISCAS.2016.7539021\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a hardware implementation of a mantissa/exponent-based tone mapping algorithm for wide dynamic range (WDR) images. The algorithm performs tone mapping by using a global compression model for the pixel intensities combined with a local contrast enhancement model. The pixel intensities of the WDR images used in this paper are represented in a mantissa/exponent format produced by an innovative WDR imager which takes advantage of a multi-reset technique during the capture process. The algorithm has been implemented on FPGA and designed to be very small, fast, power-efficient and has the potential to be directly integrated into the same chip as the imager. Experimental results performed by using different images show that our implementation is reliable and efficient.\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"35 1\",\"pages\":\"2210-2213\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7539021\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7539021","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware implementation of a real-time tone mapping algorithm based on a mantissa-exponent representation
This paper presents a hardware implementation of a mantissa/exponent-based tone mapping algorithm for wide dynamic range (WDR) images. The algorithm performs tone mapping by using a global compression model for the pixel intensities combined with a local contrast enhancement model. The pixel intensities of the WDR images used in this paper are represented in a mantissa/exponent format produced by an innovative WDR imager which takes advantage of a multi-reset technique during the capture process. The algorithm has been implemented on FPGA and designed to be very small, fast, power-efficient and has the potential to be directly integrated into the same chip as the imager. Experimental results performed by using different images show that our implementation is reliable and efficient.