Characterizing interlayer edge placement with SEM contours

Abstract. Background: The continuous scaling of integrated circuit requires not only a very good control of the device critical dimensions but also a very accurate control of the device overlay between layers to achieve satisfactory yields. These two critical factors can be combined to a single metric called interlayer edge placement error (EPEinterlayer) that quantifies the process margin necessary to keep a safe separation, extension, or overlap between the edges of a pattern in one layer with respect to another pattern in a second layer. Aim: The purpose of this work is to characterize with scanning electron microscopy (SEM), the EPEinterlayer and overlay variances of complex contact shapes relative to a poly layer to assess the contributions of the systematic and random EPEinterlayer. Approach: SEM images of a few etched patterns were recorded sequentially for both contact and poly features at the same locations on the wafer. Then, SEM contours were extracted, aligned, and overlapped to derive EPEinterlayer. One experiment was focusing on intrawafer EPEinterlayer characterization whereas another was studying more specifically intrafield overlay variations. For the latter experiment, systematic overlay errors were added to facilitate the comparison of the SEM-based method with respect to a reference image-based overlay (IBO) method. Results: The earliest direct metrology of EPEinterlayer and overlay in device enabled by this work shows a very high variability of EPEinterlayer and overlay errors across wafer and across field. Conclusions: By directly measuring the EPEinterlayer on devices that are not accessible by the standard method (optical IBO on OL structures), we showed the feasibility of this metrology and observed more dimensional variance in devices than recognized with IBO, thereby enabling better control of device pattern variation.