K. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Rucker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H. Wulf, R. Pazirandeh, N. Ilkov
{"title":"采用0.25 /spl mu/m SiGe:C BiCMOS技术的5 nm栅极氧化物的高性能RF LDMOS晶体管","authors":"K. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Rucker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H. Wulf, R. Pazirandeh, N. Ilkov","doi":"10.1109/IEDM.2001.979657","DOIUrl":null,"url":null,"abstract":"We demonstrate high performance RF LDMOS transistors integrated into an advanced industrial 0.25 /spl mu/m BiCMOS process with only one additional mask level. These devices have minimum 0.25 /spl mu/m physical gate lengths, use the 5 nm standard gate oxide of the logic transistors, and show f/sub T/ and f/sub max/ values of up to 30 and 50 GHz, respectively. The breakdown voltages are between 26 V and 13 V depending on layout. The power-added efficiency (PAE) is 70% at 560 mW/2 GHz and 60% at 340 mW/5 GHz.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"9 1","pages":"40.4.1-40.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"High performance RF LDMOS transistors with 5 nm gate oxide in a 0.25 /spl mu/m SiGe:C BiCMOS technology\",\"authors\":\"K. Ehwald, B. Heinemann, W. Roepke, W. Winkler, H. Rucker, F. Fuernhammer, D. Knoll, R. Barth, B. Hunger, H. Wulf, R. Pazirandeh, N. Ilkov\",\"doi\":\"10.1109/IEDM.2001.979657\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrate high performance RF LDMOS transistors integrated into an advanced industrial 0.25 /spl mu/m BiCMOS process with only one additional mask level. These devices have minimum 0.25 /spl mu/m physical gate lengths, use the 5 nm standard gate oxide of the logic transistors, and show f/sub T/ and f/sub max/ values of up to 30 and 50 GHz, respectively. The breakdown voltages are between 26 V and 13 V depending on layout. The power-added efficiency (PAE) is 70% at 560 mW/2 GHz and 60% at 340 mW/5 GHz.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"9 1\",\"pages\":\"40.4.1-40.4.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2001.979657\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2001.979657","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance RF LDMOS transistors with 5 nm gate oxide in a 0.25 /spl mu/m SiGe:C BiCMOS technology
We demonstrate high performance RF LDMOS transistors integrated into an advanced industrial 0.25 /spl mu/m BiCMOS process with only one additional mask level. These devices have minimum 0.25 /spl mu/m physical gate lengths, use the 5 nm standard gate oxide of the logic transistors, and show f/sub T/ and f/sub max/ values of up to 30 and 50 GHz, respectively. The breakdown voltages are between 26 V and 13 V depending on layout. The power-added efficiency (PAE) is 70% at 560 mW/2 GHz and 60% at 340 mW/5 GHz.
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