{"title":"JPEG 2000的快速EBCOT编码器架构","authors":"Somya Rathi, Zhongfeng Wang","doi":"10.1109/SIPS.2007.4387616","DOIUrl":null,"url":null,"abstract":"Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"31 1","pages":"595-599"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Fast EBCOT Encoder Architecture for JPEG 2000\",\"authors\":\"Somya Rathi, Zhongfeng Wang\",\"doi\":\"10.1109/SIPS.2007.4387616\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.\",\"PeriodicalId\":93225,\"journal\":{\"name\":\"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)\",\"volume\":\"31 1\",\"pages\":\"595-599\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2007.4387616\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2007.4387616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.