Macromodeling of realistic single electron transistors for large scale circuit simulation

In this paper we develop the macromodeling of single electron transistor (SET) based on the actual experiment results and the proposed model. Single electron transistors are supposed to be among the top candidates for the kernel devices of logic circuits in the post-CMOS period of near future. To develop an efficient model can be very useful for the simulation of large scale SET circuit. This model which is less time-consuming and reproduce the actual experiment results reasonably is fit for the simulation of SET circuit.