An ultra-low voltage, VCO-based ADC with digital background calibration

This paper introduces an ultra-low voltage open loop VCO-based ADC with background calibration for ultra-low power applications. A novel calibration scheme is proposed to calibrate the nonlinear voltage-to-frequency tuning curve of the VCO. A replica VCO is used to compute the correction coefficients and the corrected values are stored in a lookup table. The proposed calibration method is at least 64 times faster than other state-of-the-art ones. A test chip was implemented in commercial 65nm CMOS technology. Measurement results confirm the effectiveness of the calibration scheme at 0.4 V. The proposed VCO-based ADC achieves a resolution of 8.8 bits at 10 KHz bandwidth with the power consumption of 1.15 μW in the open loop architecture.