N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Zhihong Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke
{"title":"通过对变异源的描述和管理,实现了稳健的TSV中路和中路流程集成","authors":"N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Zhihong Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke","doi":"10.1109/ECTC.2012.6248922","DOIUrl":null,"url":null,"abstract":"An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.","PeriodicalId":6384,"journal":{"name":"2012 IEEE 62nd Electronic Components and Technology Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation\",\"authors\":\"N. Kumar, S. Ramaswami, J. Dukovic, J. Tseng, R. Ding, N. Rajagopalan, B. Eaton, R. Mishra, R. Yalamanchili, Zhihong Wang, S. Xia, K. Sapre, J. Hua, A. Chan, G. Mori, B. Linke\",\"doi\":\"10.1109/ECTC.2012.6248922\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.\",\"PeriodicalId\":6384,\"journal\":{\"name\":\"2012 IEEE 62nd Electronic Components and Technology Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-07-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 62nd Electronic Components and Technology Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2012.6248922\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 62nd Electronic Components and Technology Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2012.6248922","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation
An overview is given of developments in unit-process and process-integration technology enabling the realization of through-silicon vias (TSVs) for 3D chip stacking. TSVs are expected to increase interconnect bandwidth, reduce wire delay due to shorter vertical signal path, and improve power efficiency [1-3]. The fabrication sequences for forming TSVs in the middle of the line (via-middle approach) and for revealing them from the backside in the far back end of the line are described with detailed attention to major unit processes of etch, dielectric deposition, barrier and seed deposition, electrochemical deposition, and chemical-mechanical planarization. Unit-process advances are described in relation to the structural and functional requirements of the TSVs, and examples are given of co-optimization among the interdependent steps of the integrated sequence. Emphasis is given to copper vias of diameter 4 to 10μm with aspect ratio between 8 and 12. For both the viaformation and via-reveal sequence, it is shown how integration problems were overcome by a comprehensive approach.