{"title":"静态定时分析中一种快速准确的共径悲观消除方法","authors":"Baihong Jin, Guojie Luo, Wentai Zhang","doi":"10.1109/ISCAS.2016.7539131","DOIUrl":null,"url":null,"abstract":"The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest [1].","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 1","pages":"2623-2626"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A fast and accurate approach for common path pessimism removal in static timing analysis\",\"authors\":\"Baihong Jin, Guojie Luo, Wentai Zhang\",\"doi\":\"10.1109/ISCAS.2016.7539131\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest [1].\",\"PeriodicalId\":6546,\"journal\":{\"name\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"volume\":\"6 1\",\"pages\":\"2623-2626\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Symposium on Circuits and Systems (ISCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2016.7539131\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2016.7539131","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fast and accurate approach for common path pessimism removal in static timing analysis
The dual-mode delay model, while being effective for characterizing on-chip timing variations, also yields timing analysis results that are overly pessimistic due to the Common Path Pessimism (CPP). In this paper, we develop a fast and accurate block-based algorithm for removing this pessimism in timing analysis, when the dual-mode delay model is used. We illustrate the effectiveness of our algorithm on a set of benchmarks from the TAU 2014 Contest [1].
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