{"title":"基于Spin-MTJ的非易失性触发器","authors":"Weisheng Zhao, E. Belhaire, C. Chappert","doi":"10.1109/NANO.2007.4601218","DOIUrl":null,"url":null,"abstract":"Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.","PeriodicalId":6415,"journal":{"name":"2007 7th IEEE Conference on Nanotechnology (IEEE NANO)","volume":"24 1","pages":"399-402"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"86","resultStr":"{\"title\":\"Spin-MTJ based Non-volatile Flip-Flop\",\"authors\":\"Weisheng Zhao, E. Belhaire, C. Chappert\",\"doi\":\"10.1109/NANO.2007.4601218\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.\",\"PeriodicalId\":6415,\"journal\":{\"name\":\"2007 7th IEEE Conference on Nanotechnology (IEEE NANO)\",\"volume\":\"24 1\",\"pages\":\"399-402\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"86\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th IEEE Conference on Nanotechnology (IEEE NANO)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NANO.2007.4601218\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th IEEE Conference on Nanotechnology (IEEE NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2007.4601218","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.