三维V-NAND中用于反向偏置辅助擦除结构的多层通心粉填料的演示

IF 0.5 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Journal of Semiconductor Technology and Science Pub Date : 2021-10-31 DOI:10.5573/jsts.2021.21.5.334

Dae-Han Jung, Khwang-Sun Lee, Jun-Young Park

{"title":"三维V-NAND中用于反向偏置辅助擦除结构的多层通心粉填料的演示","authors":"Dae-Han Jung, Khwang-Sun Lee, Jun-Young Park","doi":"10.5573/jsts.2021.21.5.334","DOIUrl":null,"url":null,"abstract":"—Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing density. However, potential transfer through the silicon substrate or metal bit-line (BL) is insufficient with the increased number of stacks. Hence, we propose a novel V-NAND structure including multi-layered macaroni filler. The proposed macaroni filler is composed of a dielectric outer layer and a metallic core layer. The metallic core layer makes back-biasing is possible in V-NAND. As a result, erase speed can be improved without large modification of fabrication process or device layout.","PeriodicalId":17067,"journal":{"name":"Journal of Semiconductor Technology and Science","volume":"1 1","pages":""},"PeriodicalIF":0.5000,"publicationDate":"2021-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND\",\"authors\":\"Dae-Han Jung, Khwang-Sun Lee, Jun-Young Park\",\"doi\":\"10.5573/jsts.2021.21.5.334\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"—Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing density. However, potential transfer through the silicon substrate or metal bit-line (BL) is insufficient with the increased number of stacks. Hence, we propose a novel V-NAND structure including multi-layered macaroni filler. The proposed macaroni filler is composed of a dielectric outer layer and a metallic core layer. The metallic core layer makes back-biasing is possible in V-NAND. As a result, erase speed can be improved without large modification of fabrication process or device layout.\",\"PeriodicalId\":17067,\"journal\":{\"name\":\"Journal of Semiconductor Technology and Science\",\"volume\":\"1 1\",\"pages\":\"\"},\"PeriodicalIF\":0.5000,\"publicationDate\":\"2021-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Semiconductor Technology and Science\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.5573/jsts.2021.21.5.334\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Semiconductor Technology and Science","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.5573/jsts.2021.21.5.334","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 1

摘要

控制NAND闪存的擦除速度是存储技术的挑战之一。随着平面NAND闪存向垂直集成栅极全能(GAA)技术的发展，为了获得更好的封装密度，需要增加字线(WL)堆叠数。然而，随着堆叠数量的增加，通过硅衬底或金属位线(BL)的电位传递不足。因此，我们提出了一种包含多层通心粉填料的新型V-NAND结构。所提出的通心粉填料由介电外层和金属芯层组成。金属芯层使得v型nand的背偏成为可能。因此，擦除速度可以提高，而无需对制造工艺或器件布局进行大的修改。

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Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND

—Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing density. However, potential transfer through the silicon substrate or metal bit-line (BL) is insufficient with the increased number of stacks. Hence, we propose a novel V-NAND structure including multi-layered macaroni filler. The proposed macaroni filler is composed of a dielectric outer layer and a metallic core layer. The metallic core layer makes back-biasing is possible in V-NAND. As a result, erase speed can be improved without large modification of fabrication process or device layout.

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来源期刊

Journal of Semiconductor Technology and Science ENGINEERING, ELECTRICAL & ELECTRONIC-PHYSICS, APPLIED

CiteScore

0.90

自引率

0.00%

发文量

审稿时长

6-12 weeks

期刊介绍： Journal of Semiconductor Technology and Science is published to provide a forum for R&D people involved in every aspect of the integrated circuit technology, i.e., VLSI fabrication process technology, VLSI device technology, VLSI circuit design and other novel applications of this mass production technology. When IC was invented, these people worked together in one place. However, as the field of IC expanded, our individual knowledge became narrower, creating different branches in the technical society, which has made it more difficult to communicate as a whole. The fisherman, however, always knows that he can capture more fish at the border where warm and cold-water meet. Thus, we decided to go backwards gathering people involved in all VLSI technology in one place.