S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah
{"title":"代工TSV集成与制造挑战","authors":"S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah","doi":"10.1109/IITC.2014.6831840","DOIUrl":null,"url":null,"abstract":"Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.","PeriodicalId":6823,"journal":{"name":"2021 IEEE International Interconnect Technology Conference (IITC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Foundry TSV integration and manufacturing challenges\",\"authors\":\"S. Gong, Wei Liu, Juan Boon Tan, Mahesh Bhatkar, H. Cong, J. Oswald, E. Lo, S. Siah\",\"doi\":\"10.1109/IITC.2014.6831840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.\",\"PeriodicalId\":6823,\"journal\":{\"name\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE International Interconnect Technology Conference (IITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC.2014.6831840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Interconnect Technology Conference (IITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC.2014.6831840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Foundry TSV integration and manufacturing challenges
Foundry integration and manufacturing challenges for 2.5D TSV technology are discussed, with focus on in-line defectivity and warpage control. The major defect types and yield correlation are scrutinized. The results show that Cu out-diffusion from TSV due to oxide liner isolation defects has a bigger impact on yield compared to open TSV. The model suggests that one redundant TSV is enough to mitigate open and leakage risks. Interposer warpage behavior is also discussed. It can be influenced by related TSV process modules and optimization can be achieved to minimize the stress induced failures at wafer and die assembly levels. In-line defectivity, wafer warpage and electrical monitoring are essential for yield projection and manufacturing consistency.