J. Kye, Hoonki Kim, J. Lim, Seungyoung Lee, Jonghoon Jung, T. Song
{"title":"先进FinFET节点的智能缩放技术","authors":"J. Kye, Hoonki Kim, J. Lim, Seungyoung Lee, Jonghoon Jung, T. Song","doi":"10.1109/VLSIT.2018.8510675","DOIUrl":null,"url":null,"abstract":"Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"119 1","pages":"149-150"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Smart scaling technology for advanced FinFET node\",\"authors\":\"J. Kye, Hoonki Kim, J. Lim, Seungyoung Lee, Jonghoon Jung, T. Song\",\"doi\":\"10.1109/VLSIT.2018.8510675\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.\",\"PeriodicalId\":6561,\"journal\":{\"name\":\"2018 IEEE Symposium on VLSI Technology\",\"volume\":\"119 1\",\"pages\":\"149-150\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2018.8510675\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2018.8510675","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Because of the complexity of technology the level of engagement between technology and design has been increased more than ever before. Design technology co-optimization (DTCO) is used to describe the process of making with competitive power, performance, area, and yield (PPAY) in various applications. This paper describes smart scaling technologies for advanced FinFET node to make technology more competitive.
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