A. Andreou, Andrew A. Dykman, Kate D. Fischl, Guillaume Garreau, Daniel R. Mendat, G. Orchard, A. Cassidy, P. Merolla, J. Arthur, Rodrigo Alvarez-Icaza, Bryan L. Jackson, D. Modha
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The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"26 1","pages":"2911-2911"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Real-time sensory information processing using the TrueNorth Neurosynaptic System\",\"authors\":\"A. Andreou, Andrew A. Dykman, Kate D. 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引用次数: 12
摘要
只提供摘要形式。IBM TrueNorth (TN)神经突触系统是一种芯片多处理器,具有紧密耦合的处理器/内存架构,可实现节能的神经计算,是30多年来神经形态工程的重要里程碑!它由4096个核心组成,每个核心都有65K的本地内存(6T SRAM)——突触——和256个算术逻辑单元——神经元——它们以一个数表示操作,并通过最多19位的计数进行计算。这些核心是使用自定义异步和同步逻辑的事件驱动的,它们通过异步分组交换的片上网状网络(NOC)进行全局连接。芯片开发板包括zynxilinx FPGA,它通过以太网UDP接口提供标准通信支持。NOC中的异步寻址事件表示(AER)也公开给用户,以便通过带有捆绑数据全双工接口的数据包连接到基于AER的外设。在系统总线上表示的一元数据值可以采用各种各样的空间和时间编码方案。脉冲密度编码(事件数Ne表示数字N)、温度计编码、时隙编码和随机编码都是例子。额外的低电平接口可用于直接与TrueNorth芯片通信,以帮助编程和参数设置。一种分层的组合编程语言Corelet可用于帮助TN应用程序的开发。IBM提供了支持和一个开发系统,以及一个可扩展的模拟器“Compass”。软件环境在标准Linux安装(Red Hat, CentOS和Ubuntu)下运行,并具有与Matlab和用于训练深度神经网络模型的Caffe的标准接口。TN架构可以使用原生AER与许多经过多年神经形态工程(硅视网膜和硅耳蜗)开发的仿生感官设备进行接口。此外,该体系结构非常适合在计算机视觉、语音识别和语言处理等领域实现深度神经网络。在感官信息处理系统架构中,既需要空间和时间上的模式处理来提取符号子空间中的特征,又需要自然语言处理来以先验的形式提供上下文和语义信息。在本文中,我们讨论了使用TN架构在三个不同领域进行的实时感官信息处理实验工作的结果(i)空间模式处理-计算机视觉(ii)时间模式处理-语音处理和识别(iii)自然语言处理-词相似度-。在ISCAS 2016上,将使用TN系统和基于听觉(硅耳蜗)和视觉(硅视网膜)的神经形态事件传感器进行实时演示。
Real-time sensory information processing using the TrueNorth Neurosynaptic System
Summary form only given. The IBM TrueNorth (TN) Neurosynaptic System, is a chip multi processor with a tightly coupled processor/memory architecture, that results in energy efficient neurocomputing and it is a significant milestone to over 30 years of neuromorphic engineering! It comprises of 4096 cores each core with 65K of local memory (6T SRAM)-synapses- and 256 arithmetic logic units - neurons-that operate on a unary number representation and compute by counting up to a maximum of 19 bits. The cores are event-driven using custom asynchronous and synchronous logic, and they are globally connected through an asynchronous packet switched mesh network on chip (NOC). The chip development board, includes a Zyng Xilinx FPGA that does the housekeeping and provides support for standard communication support through an Ethernet UDP interface. The asynchronous Addressed Event Representation (AER) in the NOC is al so exposed to the user for connection to AER based peripherals through a packet with bundled data full duplex interface. The unary data values represented on the system buses can take on a wide variety of spatial and temporal encoding schemes. Pulse density coding (the number of events Ne represents a number N), thermometer coding, time-slot encoding, and stochastic encoding are examples. Additional low level interfaces are available for communicating directly with the TrueNorth chip to aid programming and parameter setting. A hierarchical, compositional programming language, Corelet, is available to aid the development of TN applications. IBM provides support and a development system as well as “Compass” a scalable simulator. The software environment runs under standard Linux installations (Red Hat, CentOS and Ubuntu) and has standard interfaces to Matlab and to Caffe that is employed to train deep neural network models. The TN architecture can be interfaced using native AER to a number of bio-inspired sensory devices developed over many years of neuromorphic engineering (silicon retinas and silicon cochleas). In addition the architecture is well suited for implementing deep neural networks with many applications in computer vision, speech recognition and language processing. In a sensory information processing system architecture one desires both pattern processing in space and time to extract features in symbolic sub-spaces as well as natural language processing to provide contextual and semantic information in the form of priors. In this paper we discuss results from ongoing experimental work on real-time sensory information processing using the TN architecture in three different areas (i) spatial pattern processing -computer vision(ii) temporal pattern processing -speech processing and recognition(iii) natural language processing -word similarity-. A real-time demonstration will be done at ISCAS 2016 using the TN system and neuromorphic event based sensors for audition (silicon cochlea) and vision (silicon retina).