B. Lee, Jong-ryeol Yoo, Deok-Hyung Lee, Cheol Kim, I.S. Jung, Siyoung Choi, U. Chung, J. Moon
{"title":"高性能单元技术，采用低于100nm的DRAM，具有多千兆密度","authors":"B. Lee, Jong-ryeol Yoo, Deok-Hyung Lee, Cheol Kim, I.S. Jung, Siyoung Choi, U. Chung, J. Moon","doi":"10.1109/IEDM.2002.1175967","DOIUrl":null,"url":null,"abstract":"Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.","PeriodicalId":74909,"journal":{"name":"Technical digest. International Electron Devices Meeting","volume":"411 1","pages":"835-838"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High performance cell technology featuring sub-100nm DRAM with multi-gigabit density\",\"authors\":\"B. Lee, Jong-ryeol Yoo, Deok-Hyung Lee, Cheol Kim, I.S. Jung, Siyoung Choi, U. Chung, J. Moon\",\"doi\":\"10.1109/IEDM.2002.1175967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.\",\"PeriodicalId\":74909,\"journal\":{\"name\":\"Technical digest. International Electron Devices Meeting\",\"volume\":\"411 1\",\"pages\":\"835-838\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Technical digest. International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2002.1175967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Technical digest. International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2002.1175967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance cell technology featuring sub-100nm DRAM with multi-gigabit density
Fully metal embedded cell technologies, including poly-Si/W/sub x/N/W gate, Co salicide with elevated source/drain using UHV-selective epitaxial growth and CVD-W cell pad has been integrated successfully for the first time for 100 nm design rule DRAM devices. Each key technology exhibits excellent performance.
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