J. Hergenrother, G. Wilk, T. Nigam, F. Klemens, D. Monroe, P. Silverman, T. Sorsch, B. Busch, M. Green, M. R. Baker, T. Boone, M. Bude, N. A. Ciampa, E. Ferry, A. Fiory, S. Hillenius, D. Jacobson, R.W. Johnson, P. Kalavade, R. Keller, C. King, A. Kornblit, H. Krautter, J.T.-C. Lee, W. Mansfield, J. Miner, M. Morris, S. Oh, J. Rosamilia, B. Sapjeta, K. Short, K. Steiner, D. Muller, P. Voyles, J. Grazul, E. Shero, M. Givens, C. Pomarede, M. Mazanec, C. Werkhoven
{"title":"采用ALD HfO/sub 2/和Al/sub 2/O/sub 3/栅极电介质的50 nm垂直替代栅(VRG) nmosfet","authors":"J. Hergenrother, G. Wilk, T. Nigam, F. Klemens, D. Monroe, P. Silverman, T. Sorsch, B. Busch, M. Green, M. R. Baker, T. Boone, M. Bude, N. A. Ciampa, E. Ferry, A. Fiory, S. Hillenius, D. Jacobson, R.W. Johnson, P. Kalavade, R. Keller, C. King, A. Kornblit, H. Krautter, J.T.-C. Lee, W. Mansfield, J. Miner, M. Morris, S. Oh, J. Rosamilia, B. Sapjeta, K. Short, K. Steiner, D. Muller, P. Voyles, J. Grazul, E. Shero, M. Givens, C. Pomarede, M. Mazanec, C. Werkhoven","doi":"10.1109/IEDM.2001.979400","DOIUrl":null,"url":null,"abstract":"We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.","PeriodicalId":13825,"journal":{"name":"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)","volume":"71 1","pages":"3.1.1-3.1.4"},"PeriodicalIF":0.0000,"publicationDate":"2001-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics\",\"authors\":\"J. Hergenrother, G. Wilk, T. Nigam, F. Klemens, D. Monroe, P. Silverman, T. Sorsch, B. Busch, M. Green, M. R. Baker, T. Boone, M. Bude, N. A. Ciampa, E. Ferry, A. Fiory, S. Hillenius, D. Jacobson, R.W. Johnson, P. Kalavade, R. Keller, C. King, A. Kornblit, H. Krautter, J.T.-C. Lee, W. Mansfield, J. Miner, M. Morris, S. Oh, J. Rosamilia, B. Sapjeta, K. Short, K. Steiner, D. Muller, P. Voyles, J. Grazul, E. Shero, M. Givens, C. Pomarede, M. Mazanec, C. Werkhoven\",\"doi\":\"10.1109/IEDM.2001.979400\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.\",\"PeriodicalId\":13825,\"journal\":{\"name\":\"International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)\",\"volume\":\"71 1\",\"pages\":\"3.1.1-3.1.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting. Technical Digest (Cat. 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50 nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics
We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.
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