J. Warnock, J. Cressler, P. Coane, K. Chiong, M. Rothwell, K. Jenkins, J. Burghartz, E. Petrillo, N. Mazzeo, A. Megdanis, F. Hohn, M. Thomson, J. Sun, D. Tang
{"title":"全电子束0.25 μ m双极技术，ECL栅极延迟低于25 ps","authors":"J. Warnock, J. Cressler, P. Coane, K. Chiong, M. Rothwell, K. Jenkins, J. Burghartz, E. Petrillo, N. Mazzeo, A. Megdanis, F. Hohn, M. Thomson, J. Sun, D. Tang","doi":"10.1109/IEDM.1991.235267","DOIUrl":null,"url":null,"abstract":"Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.<<ETX>>","PeriodicalId":13885,"journal":{"name":"International Electron Devices Meeting 1991 [Technical Digest]","volume":"19 1","pages":"956-958"},"PeriodicalIF":0.0000,"publicationDate":"1991-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay\",\"authors\":\"J. Warnock, J. Cressler, P. Coane, K. Chiong, M. Rothwell, K. Jenkins, J. Burghartz, E. Petrillo, N. Mazzeo, A. Megdanis, F. Hohn, M. Thomson, J. Sun, D. Tang\",\"doi\":\"10.1109/IEDM.1991.235267\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.<<ETX>>\",\"PeriodicalId\":13885,\"journal\":{\"name\":\"International Electron Devices Meeting 1991 [Technical Digest]\",\"volume\":\"19 1\",\"pages\":\"956-958\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 1991 [Technical Digest]\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1991.235267\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 1991 [Technical Digest]","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1991.235267","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A full E-beam 0.25 mu m bipolar technology with sub-25 ps ECL gate delay
Summary form only given. The full leverage offered by E-beam lithography has been exploited in a 0.25- mu m bipolar process. The tight overlay capability was shown to provide a significant advantage in shrinking the overall transistor size. In conjunction with a device technology optimized to provide a 33-GHz 0.25- mu m-emitter device, this culminated in the achievement of an ECL (emitter coupled logic) delay of 24 ps at a switching current of only 1.1 mA.<>
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