用于高频DDR dram的倾斜和抖动抑制DLL体系结构

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852857

T. Hamamoto, S. Kawasaki, K. Furutani, K. Yasuda, Y. Konishi

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引用次数: 9

摘要

本文演示了用于超过400mbps运行DDR dram的倾斜和抖动抑制延迟锁环(DLL)架构。介绍了两种新的副本调整技术，减少了外部时钟和数据输出之间的定时偏差。介绍了一种改进的延迟线结构，实现了高频抑制抖动的动态链接库。

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A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs

This paper demonstrates a skew and jitter suppressed delay locked loop (DLL) architecture used for over 400 Mbps operating DDR SDRAMs. Two novel replica adjusting techniques are introduced, which reduce timing skews between external clocks and data outputs. An improved delay line architecture is introduced, which realizes a high frequency and jitter suppressed DLL.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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