A Time-Interleaved 2b/Cycle SAR ADC with Background Offset Calibration

A novel method for a two way offset calibration for an interleaved 2bit/cycle SAR based ADC is proposed. The offset mismatch between the interleaved sub-ADCs is cancelled using a background calibration circuit. Using the same circuit, the offset mismatch between the comparators used in the 2-bit per cycle SAR based sub-ADC's are cancelled at the same time. The technique is realized using a Reference comparator that sets the target offset for all comparators in all sub-ADCs. Using the proposed technique, a 1 GS/s 6-bit 2b/cycle SAR ADC is designed in 65 nm CMOS technology. The ADC consumes 3.36 mW from a 1.2 V supply voltage and achieves signal-to-noise-and-distortion ratio (SNDR) of 37.41 dB and figure of merit (FoM) of 55.49 fJ/Conv.Step at Nyquist frequency input. The FoM with mean SNDR derived from Monte-Carlo simulation is 60.42 fJ/Conv.Step. The proposed technique offers 4.5 dB improvement on average over a non-calibrated SAR ADC based on 1000 Monte-Carlo simulations.