S. Fung, M. Khare, D. Schepis, Woo-Hyeong Lee, S. Ku, H. Park, J. Snare, B. Doris, A. Ajmera, K. Muller, P. Agnello, P. Gilbert, J. Welser
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Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology
High performance SOI CMOS designed for the 100 nm technology node is presented. At 1 V supply voltage, the 33 nm devices give a drive current of 1000 (1100) /spl mu/A//spl mu/m DC (dynamic) for NFET and 445 (457) /spl mu/A//spl mu/m for PFET at an off current of 300 nA//spl mu/m. The intrinsic gate delays are 0.55 ps and 1.19 ps. The NFET delay is further reduced to 0.45 ps at gate length scaled to 25 nm. The delay and current values are the best ever reported at 1.0 V. The excellent result is accomplished by using super-HALO design on 45 nm SOI substrate.
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