Sub - 1v - 5ghz波段上下转换混频器内核，采用0.35-/spl mu/m CMOS

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103) Pub Date : 2000-06-15 DOI:10.1109/VLSIC.2000.852861

T. Wakimoto, T. Hatano, C. Yamaguchi, H. Morimura, S. Konaka

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引用次数: 3

摘要

为了降低无线通信系统射频前端的电源电压和功耗，提出了一种双平衡方律MOSFET混频器。它适用于上下转换混频器铁芯。在0.35-/spl mu/m CMOS工艺中实现，上转换混频器核心在5 ghz频段工作，电源电压为0.5 V，电源电流为0.8 mA。局部漏电抑制在- 40dbc以下。下变频混频器芯在同一频段从1 v电源消耗0.4 mA。转换增益为6db，三阶输入参考截距点(IIP3)为+ 5dbm。

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Sub 1-V 5-GHz-band up- and down-conversion mixer cores in 0.35-/spl mu/m CMOS

To lower the supply voltage and reduce the power dissipation of the RF front-end of wireless communication systems, a double-balanced square-law MOSFET mixer is proposed. It is applied to up- and down-conversion mixer cores. Implemented in a 0.35-/spl mu/m CMOS process, the up-conversion mixer core operates with a supply voltage of 0.5 V and a supply current of 0.8 mA in the 5-GHz band. The local leakage is suppressed below -40 dBc. The down-conversion mixer core drains 0.4 mA from a 1-V supply in the same band. The conversion gain is 6 dB and the 3rd-order input-referred intercept point (IIP3) is +5 dBm.

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2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

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