基于Shannon全加法器的可控加减法单元设计

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy Pub Date : 2015-04-08 DOI:10.15662/IJAREEIE.2015.0402033

S. Choubey, Rajesh Kumar Paul

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引用次数: 0

摘要

本文讨论了基于香农的全加法器和通管逻辑的可控加减法单元的设计。所提出的加法器仅使用14个晶体管来实现完整的加法器。利用Microwind 3.1和DSCH 2 VLSI CAD工具以及BSIM 4进行仿真，对各特征进行参数化分析。本文从功耗、时延、占用面积等方面进行了分析，并与前人的研究结果进行了比较。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design of Controlled Adder /Subtractor CellUsing Shannon Based Full Adder

This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.

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International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy

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