使用多线程应用程序接口在多核中央处理器上高效并行化数据包分类算法

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mahdi Abbasi, Milad Rafiee
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引用次数: 1

摘要

根据多个参数(如发送方和接收方地址)对网络分组进行分类称为分组分类。数据包分类是基于软件定义网络(SDN)的网络应用程序的核心。由于网络流量的速度不断增加,迫切需要以更高的速度进行分组分类。尽管可以通过硬件实现来加速分组分类算法,但这种解决方案成本高昂,开发能力有限。另一方面,目前解决这个问题的软件方法相对较慢。这个问题的一个实际解决方案是使用多核处理器并行化数据包分类。在本研究中,研究并实现了线程、并行模式库(PPL)、开放多处理(OpenMP)和线程构建块(TBB)库,以并行化三种分组分类算法,即元组空间搜索、元组修剪搜索和层次树。结果表明,算法和规则集的类型可能会影响并行化库的性能。通常,由于使用了盗窃机制,基于TBB的方法在并行化库中表现出最佳性能,并且在具有四核处理器的系统上可以将分类过程加速8.3倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Efficient parallelisation of the packet classification algorithms on multi-core central processing units using multi-threading application program interfaces

Efficient parallelisation of the packet classification algorithms on multi-core central processing units using multi-threading application program interfaces

The categorisation of network packets according to multiple parameters such as sender and receiver addresses is called packet classification. Packet classification lies at the core of Software-Defined Networking (SDN)-based network applications. Due to the increasing speed of network traffic, there is an urgent need for packet classification at higher speeds. Although it is possible to accelerate packet classification algorithms through hardware implementation, this solution imposes high costs and offers limited development capacity. On the other hand, current software methods to solve this problem are relatively slow. A practical solution to this problem is to parallelise packet classification using multi-core processors. In this study, the Thread, parallel patterns library (PPL), open multi-processing (OpenMP), and threading building blocks (TBB) libraries are examined and implemented to parallelise three packet classification algorithms, i.e. tuple space search, tuple pruning search, and hierarchical tree. According to the results, the type of algorithm and rulesets may influence the performance of parallelisation libraries. In general, the TBB-based method shows the best performance among parallelisation libraries due to using a theft mechanism and can accelerate the classification process up to 8.3 times on a system with a quad-core processor.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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