利用系数对称设计低复杂度并行多相有限脉冲响应滤波器

IF 1 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Konudula Anjali Rao, Abhishek Kumar, Dmitrii Kaplun, Sujit Kumar Patel, Neetesh Purohit
{"title":"利用系数对称设计低复杂度并行多相有限脉冲响应滤波器","authors":"Konudula Anjali Rao,&nbsp;Abhishek Kumar,&nbsp;Dmitrii Kaplun,&nbsp;Sujit Kumar Patel,&nbsp;Neetesh Purohit","doi":"10.1049/cds2.12134","DOIUrl":null,"url":null,"abstract":"<p>In this correspondence, a mathematical model is developed for the efficient realisation of a generalised <i>M</i> × <i>M</i> polyphase parallel finite impulse response (FIR) filter structure composed of <i>M</i> parallel conventional decimator polyphase filters. Primarily, the proposed structure is designed in such a way that the benefit of coefficient symmetry property of linear-phase FIR filters can be availed without using the pre/post circuit blocks. A numerical example is also studied to validate the proposed structure. Furthermore, the delay-elements reduction approach is given to avoid the excessive usage of memory elements and the performance of the proposed structure is evaluated in terms of the number of delay elements <math>\n <semantics>\n <mrow>\n <mo>(</mo>\n <mrow>\n <mi>D</mi>\n </mrow>\n <mo>)</mo>\n </mrow>\n <annotation> $(\\mathcal{D})$</annotation>\n </semantics></math>, adders <math>\n <semantics>\n <mrow>\n <mo>(</mo>\n <mrow>\n <mi>A</mi>\n </mrow>\n <mo>)</mo>\n </mrow>\n <annotation> $(\\mathcal{A})$</annotation>\n </semantics></math> and multipliers <math>\n <semantics>\n <mrow>\n <mo>(</mo>\n <mrow>\n <mi>M</mi>\n </mrow>\n <mo>)</mo>\n </mrow>\n <annotation> $(\\mathcal{M})$</annotation>\n </semantics></math>. Compared to the traditional structures, our proposed structure is found to be more efficient in terms of <math>\n <semantics>\n <mrow>\n <mi>M</mi>\n </mrow>\n <annotation> $\\mathcal{M}$</annotation>\n </semantics></math>. Moreover, in contrast to the fast FIR algorithms, the proposed structure resolves the issues of additional requirements of the pre/post blocks and the absence of parallel structure with coefficient symmetry for higher prime values of <i>M</i> (i.e. <i>M</i> &gt; 3). The synthesis result reveals that the proposed 37-tap filter (with <i>M</i> = 3 and 12-bit inputs) involves 30% less area-delay-product (ADP) per output and 33.05% less power per output compared to the most recent structure.</p>","PeriodicalId":50386,"journal":{"name":"Iet Circuits Devices & Systems","volume":null,"pages":null},"PeriodicalIF":1.0000,"publicationDate":"2022-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12134","citationCount":"1","resultStr":"{\"title\":\"Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry\",\"authors\":\"Konudula Anjali Rao,&nbsp;Abhishek Kumar,&nbsp;Dmitrii Kaplun,&nbsp;Sujit Kumar Patel,&nbsp;Neetesh Purohit\",\"doi\":\"10.1049/cds2.12134\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>In this correspondence, a mathematical model is developed for the efficient realisation of a generalised <i>M</i> × <i>M</i> polyphase parallel finite impulse response (FIR) filter structure composed of <i>M</i> parallel conventional decimator polyphase filters. Primarily, the proposed structure is designed in such a way that the benefit of coefficient symmetry property of linear-phase FIR filters can be availed without using the pre/post circuit blocks. A numerical example is also studied to validate the proposed structure. Furthermore, the delay-elements reduction approach is given to avoid the excessive usage of memory elements and the performance of the proposed structure is evaluated in terms of the number of delay elements <math>\\n <semantics>\\n <mrow>\\n <mo>(</mo>\\n <mrow>\\n <mi>D</mi>\\n </mrow>\\n <mo>)</mo>\\n </mrow>\\n <annotation> $(\\\\mathcal{D})$</annotation>\\n </semantics></math>, adders <math>\\n <semantics>\\n <mrow>\\n <mo>(</mo>\\n <mrow>\\n <mi>A</mi>\\n </mrow>\\n <mo>)</mo>\\n </mrow>\\n <annotation> $(\\\\mathcal{A})$</annotation>\\n </semantics></math> and multipliers <math>\\n <semantics>\\n <mrow>\\n <mo>(</mo>\\n <mrow>\\n <mi>M</mi>\\n </mrow>\\n <mo>)</mo>\\n </mrow>\\n <annotation> $(\\\\mathcal{M})$</annotation>\\n </semantics></math>. Compared to the traditional structures, our proposed structure is found to be more efficient in terms of <math>\\n <semantics>\\n <mrow>\\n <mi>M</mi>\\n </mrow>\\n <annotation> $\\\\mathcal{M}$</annotation>\\n </semantics></math>. Moreover, in contrast to the fast FIR algorithms, the proposed structure resolves the issues of additional requirements of the pre/post blocks and the absence of parallel structure with coefficient symmetry for higher prime values of <i>M</i> (i.e. <i>M</i> &gt; 3). The synthesis result reveals that the proposed 37-tap filter (with <i>M</i> = 3 and 12-bit inputs) involves 30% less area-delay-product (ADP) per output and 33.05% less power per output compared to the most recent structure.</p>\",\"PeriodicalId\":50386,\"journal\":{\"name\":\"Iet Circuits Devices & Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":1.0000,\"publicationDate\":\"2022-11-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://onlinelibrary.wiley.com/doi/epdf/10.1049/cds2.12134\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Iet Circuits Devices & Systems\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12134\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Iet Circuits Devices & Systems","FirstCategoryId":"5","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/cds2.12134","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 1

摘要

在这种对应关系中,开发了一个数学模型,用于有效地实现由M个并行传统抽取多相滤波器组成的广义M×M多相并行有限脉冲响应(FIR)滤波器结构。首先,所提出的结构是这样设计的,即在不使用前置/后置电路块的情况下,可以利用线性相位FIR滤波器的系数对称特性。通过算例验证了该结构的有效性。此外为了避免存储器元件的过度使用,给出了减少延迟元件的方法,并根据延迟元件的数量(D)$(\mathcal{D})$来评估所提出的结构的性能,加法器(A)$(\mathcal{A})$和乘法器(M)$(\mathcal{M})$。与传统结构相比,我们提出的结构在M$\mathcal{M}$方面更有效。此外,与快速FIR算法相比,所提出的结构解决了前置/后置块的附加要求以及对于M的更高素数(即M>;3)缺乏具有系数对称性的并行结构的问题。综合结果表明,与最新的结构相比,所提出的37抽头滤波器(具有M=3和12位输入)每次输出的面积延迟乘积(ADP)减少30%,每次输出的功率减少33.05%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry

Design of low complexity parallel polyphase finite impulse response filter using coefficient symmetry

In this correspondence, a mathematical model is developed for the efficient realisation of a generalised M × M polyphase parallel finite impulse response (FIR) filter structure composed of M parallel conventional decimator polyphase filters. Primarily, the proposed structure is designed in such a way that the benefit of coefficient symmetry property of linear-phase FIR filters can be availed without using the pre/post circuit blocks. A numerical example is also studied to validate the proposed structure. Furthermore, the delay-elements reduction approach is given to avoid the excessive usage of memory elements and the performance of the proposed structure is evaluated in terms of the number of delay elements ( D ) $(\mathcal{D})$ , adders ( A ) $(\mathcal{A})$ and multipliers ( M ) $(\mathcal{M})$ . Compared to the traditional structures, our proposed structure is found to be more efficient in terms of M $\mathcal{M}$ . Moreover, in contrast to the fast FIR algorithms, the proposed structure resolves the issues of additional requirements of the pre/post blocks and the absence of parallel structure with coefficient symmetry for higher prime values of M (i.e. M > 3). The synthesis result reveals that the proposed 37-tap filter (with M = 3 and 12-bit inputs) involves 30% less area-delay-product (ADP) per output and 33.05% less power per output compared to the most recent structure.

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来源期刊
Iet Circuits Devices & Systems
Iet Circuits Devices & Systems 工程技术-工程:电子与电气
CiteScore
3.80
自引率
7.70%
发文量
32
审稿时长
3 months
期刊介绍: IET Circuits, Devices & Systems covers the following topics: Circuit theory and design, circuit analysis and simulation, computer aided design Filters (analogue and switched capacitor) Circuit implementations, cells and architectures for integration including VLSI Testability, fault tolerant design, minimisation of circuits and CAD for VLSI Novel or improved electronic devices for both traditional and emerging technologies including nanoelectronics and MEMs Device and process characterisation, device parameter extraction schemes Mathematics of circuits and systems theory Test and measurement techniques involving electronic circuits, circuits for industrial applications, sensors and transducers
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