多核体系结构上优化量子电路映射的匈牙利量子比特分配

IF 1.4 3区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Pau Escofet;Anabel Ovide;Carmen G. Almudever;Eduard Alarcón;Sergi Abadal
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引用次数: 1

摘要

模块化量子计算架构为克服当前量子计算机的扩展限制提供了一个有前途的替代单片设计。为了实现超越小型原型的可扩展性,量子架构有望采用模块化方法,其特点是紧密连接的量子比特集群,这些集群之间的连接更稀疏。在多个处理核心之间有效地分配量子位对于提高量子计算系统的性能和可扩展性至关重要。为了解决这一挑战,我们提出了匈牙利量子比特分配(HQA)算法,该算法利用匈牙利算法来改进量子比特到核心的分配。HQA算法考虑了整个电路中量子比特之间的相互作用,实现了细粒度分区和增强的量子比特利用率。我们通过使用现实世界量子算法和随机量子电路的综合实验,将HQA算法与最先进的替代方案进行比较。结果表明,我们提出的方法优于现有方法,平均提高了1.28倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures
Modular quantum computing architectures offer a promising alternative to monolithic designs for overcoming the scaling limitations of current quantum computers. To achieve scalability beyond small prototypes, quantum architectures are expected to adopt a modular approach, featuring clusters of tightly connected quantum bits with sparser connections between these clusters. Efficiently distributing qubits across multiple processing cores is critical for improving quantum computing systems’ performance and scalability. To address this challenge, we propose the Hungarian Qubit Assignment (HQA) algorithm, which leverages the Hungarian algorithm to improve qubit-to-core assignment. The HQA algorithm considers the interactions between qubits over the entire circuit, enabling fine-grained partitioning and enhanced qubit utilization. We compare the HQA algorithm with state-of-the-art alternatives through comprehensive experiments using both real-world quantum algorithms and random quantum circuits. The results demonstrate the superiority of our proposed approach, outperforming existing methods, with an average improvement of 1.28×.
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来源期刊
IEEE Computer Architecture Letters
IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-
CiteScore
4.60
自引率
4.30%
发文量
29
期刊介绍: IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.
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