利用ARTEMIS求解器表征微电子电路中的传输线

IF 1.8 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Saurabh S. Sawant;Zhi Yao;Revathi Jambunathan;Andrew Nonaka
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引用次数: 2

摘要

电磁波与微电子器件相互作用的建模和表征以导出网络参数已在电子工业中得到广泛应用。然而,随着这些设备越来越小型化,具有更精细的几何特征,计算工具必须利用许多核心/GPU架构来有效地解决感兴趣的长度和时间尺度。这一直是我们开源解算器ARTEMIS(自适应网格细化时域电动力解算器)的重点,该解算器在现代基于GPU的超级计算架构上具有性能,同时可接受额外的物理耦合。这项工作展示了它在使用既定技术表征输电线路网络参数方面的用途。对该工作流程进行了严格的验证和验证,然后将其应用于分析为光子探测器应用而设计的CMOS芯片上的传输线。在最先进的GPU资源上进行数百万个时间步长的模拟,以解决千兆赫频率下的纳米级特征。网络参数用于获得作为SPICE模型输入的相位延迟和特性阻抗。该代码显示出理想的弱缩放效率,最高可达1024 GPU,2048 GPU的效率为84%,这突出了它在未来用于更大、更复杂电路设备的网络分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Characterization of Transmission Lines in Microelectronic Circuits Using the ARTEMIS Solver
Modeling and characterization of electromagnetic wave interactions with microelectronic devices to derive network parameters has been a widely used practice in the electronic industry. However, as these devices become increasingly miniaturized with finer-scale geometric features, computational tools must make use of manycore/GPU architectures to efficiently resolve length and time scales of interest. This has been the focus of our open-source solver, ARTEMIS (Adaptive mesh Refinement Time-domain ElectrodynaMIcs Solver), which is performant on modern GPU-based supercomputing architectures while being amenable to additional physics coupling. This work demonstrates its use for characterizing network parameters of transmission lines using established techniques. A rigorous verification and validation of the workflow is carried out, followed by its application for analyzing a transmission line on a CMOS chip designed for a photon-detector application. Simulations are performed for millions of timesteps on state-of-the-art GPU resources to resolve nanoscale features at gigahertz frequencies. The network parameters are used to obtain phase delay and characteristic impedance that serve as inputs to SPICE models. The code is demonstrated to exhibit ideal weak scaling efficiency up to 1024 GPUs and 84% efficiency for 2048 GPUs, which underscores its use for network analysis of larger, more complex circuit devices in the future.
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来源期刊
CiteScore
4.30
自引率
0.00%
发文量
27
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