面向实用的128位通用微体系结构

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-06-20 DOI:10.1109/LCA.2023.3287762

Chandana S. Deshpande;Arthur Perais;Frédéric Pétrot

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引用次数: 0

摘要

英特尔在2017年推出了5级分页模式，以支持57位虚拟地址空间。这一点，再加上可以通过加载和存储指令（例如，非易失性存储器）访问备份存储的模式，让我们可以设想64位地址空间不足的未来。在这种情况下，直接的解决方案是采用平坦的128位地址空间。在这封早期的信中，我们进行了高级别的实验，从而提出了一种可能的通用处理器微架构，该架构以有限的硬件成本提供128位支持。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Toward Practical 128-Bit General Purpose Microarchitectures

Intel introduced 5-level paging mode to support 57-bit virtual address space in 2017. This, coupled to paradigms where backup storage can be accessed through load and store instructions (e.g., non volatile memories), lets us envision a future in which a 64-bit address space has become insufficient. In that event, the straightforward solution would be to adopt a flat 128-bit address space. In this early stage letter, we conduct high-level experiments that lead us to suggest a possible general-purpose processor micro-architecture providing 128-bit support with limited hardware cost.

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.