{"title":"从这里去哪里?用于高码率LTE Turbo码解码的新的跨层技术","authors":"Stefan Weithoffer, N. Wehn","doi":"10.5194/ARS-16-77-2018","DOIUrl":null,"url":null,"abstract":"Abstract. The wide range of code rates and code block sizes supported by todays\nwireless communication standards, together with the requirement for a\nthroughput in the order of Gbps, necessitates sophisticated and highly\nparallel channel decoder architectures. Code rates specified in the LTE\nstandard, which uses Turbo-Codes, range up to r=0.94 to maximize the\ninformation throughput by transmitting only a minimum amount of parity\ninformation, which negatively impacts the error correcting performance. This\nespecially holds for highly parallel hardware architectures. Therefore, the\nerror correcting performance must be traded-off against the degree of\nparallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on\ncode block level to alleviate this trade-off. In this paper, we follow a\ncross-layer approach by combining system level knowledge about the\nrate-matching and the transport block structure in LTE with the bit-level\ntechnique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code\ndecoder hardware architecture achieves coding gains of 0.4–1.8 dB\ncompared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible\nhardware overhead and a resulting high area and energy efficiency and give\npost place and route synthesis numbers.\n","PeriodicalId":45093,"journal":{"name":"Advances in Radio Science","volume":" ","pages":""},"PeriodicalIF":0.9000,"publicationDate":"2018-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates\",\"authors\":\"Stefan Weithoffer, N. Wehn\",\"doi\":\"10.5194/ARS-16-77-2018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract. The wide range of code rates and code block sizes supported by todays\\nwireless communication standards, together with the requirement for a\\nthroughput in the order of Gbps, necessitates sophisticated and highly\\nparallel channel decoder architectures. Code rates specified in the LTE\\nstandard, which uses Turbo-Codes, range up to r=0.94 to maximize the\\ninformation throughput by transmitting only a minimum amount of parity\\ninformation, which negatively impacts the error correcting performance. This\\nespecially holds for highly parallel hardware architectures. Therefore, the\\nerror correcting performance must be traded-off against the degree of\\nparallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on\\ncode block level to alleviate this trade-off. In this paper, we follow a\\ncross-layer approach by combining system level knowledge about the\\nrate-matching and the transport block structure in LTE with the bit-level\\ntechnique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code\\ndecoder hardware architecture achieves coding gains of 0.4–1.8 dB\\ncompared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible\\nhardware overhead and a resulting high area and energy efficiency and give\\npost place and route synthesis numbers.\\n\",\"PeriodicalId\":45093,\"journal\":{\"name\":\"Advances in Radio Science\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":0.9000,\"publicationDate\":\"2018-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Advances in Radio Science\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.5194/ARS-16-77-2018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advances in Radio Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.5194/ARS-16-77-2018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Where to go from here? New cross layer techniques for LTE Turbo-Code decoding at high code rates
Abstract. The wide range of code rates and code block sizes supported by todays
wireless communication standards, together with the requirement for a
throughput in the order of Gbps, necessitates sophisticated and highly
parallel channel decoder architectures. Code rates specified in the LTE
standard, which uses Turbo-Codes, range up to r=0.94 to maximize the
information throughput by transmitting only a minimum amount of parity
information, which negatively impacts the error correcting performance. This
especially holds for highly parallel hardware architectures. Therefore, the
error correcting performance must be traded-off against the degree of
parallel processing. State-of-the-art Turbo-Code decoder hardware architectures are optimized on
code block level to alleviate this trade-off. In this paper, we follow a
cross-layer approach by combining system level knowledge about the
rate-matching and the transport block structure in LTE with the bit-level
technique of on-the-fly CRC calculation. Thereby, our proposed Turbo-Code
decoder hardware architecture achieves coding gains of 0.4–1.8 dB
compared to state-of-the-art accross a wide range of code block sizes. For the fully LTE compatible Turbo-Code decoder, we demonstrate a negligible
hardware overhead and a resulting high area and energy efficiency and give
post place and route synthesis numbers.