{"title":"晶片设计与异质集成封装的最新进展与趋势","authors":"J. Lau","doi":"10.1115/1.4062529","DOIUrl":null,"url":null,"abstract":"\n In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":2.2000,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Recent Advances And Trends In Chiplet Design And Heterogeneous Integration Packaging\",\"authors\":\"J. Lau\",\"doi\":\"10.1115/1.4062529\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.\",\"PeriodicalId\":15663,\"journal\":{\"name\":\"Journal of Electronic Packaging\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2023-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Electronic Packaging\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1115/1.4062529\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electronic Packaging","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1115/1.4062529","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Recent Advances And Trends In Chiplet Design And Heterogeneous Integration Packaging
In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.
期刊介绍:
The Journal of Electronic Packaging publishes papers that use experimental and theoretical (analytical and computer-aided) methods, approaches, and techniques to address and solve various mechanical, materials, and reliability problems encountered in the analysis, design, manufacturing, testing, and operation of electronic and photonics components, devices, and systems.
Scope: Microsystems packaging; Systems integration; Flexible electronics; Materials with nano structures and in general small scale systems.