晶片设计与异质集成封装的最新进展与趋势

IF 2.2 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
J. Lau
{"title":"晶片设计与异质集成封装的最新进展与趋势","authors":"J. Lau","doi":"10.1115/1.4062529","DOIUrl":null,"url":null,"abstract":"\n In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":2.2000,"publicationDate":"2023-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Recent Advances And Trends In Chiplet Design And Heterogeneous Integration Packaging\",\"authors\":\"J. Lau\",\"doi\":\"10.1115/1.4062529\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\n In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.\",\"PeriodicalId\":15663,\"journal\":{\"name\":\"Journal of Electronic Packaging\",\"volume\":\" \",\"pages\":\"\"},\"PeriodicalIF\":2.2000,\"publicationDate\":\"2023-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Journal of Electronic Packaging\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://doi.org/10.1115/1.4062529\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electronic Packaging","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1115/1.4062529","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

在这项研究中,小芯片设计和异构集成封装,特别是(a)芯片分区和异构集成(由成本和技术优化驱动),(b)芯片拆分和异构集成,将研究(d)在组装封装衬底顶部具有有机中介层的多系统和异质集成,以及(e)在组装包装衬底顶部具有硅通孔(TSV)中介层的多重系统和异质整合。项目(c)、(d)和(e)由形状因素和性能驱动。重点介绍了它们的优缺点、设计、材料、工艺和示例。还将提供一些建议。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Recent Advances And Trends In Chiplet Design And Heterogeneous Integration Packaging
In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration (driven by cost and technology optimization), (b) chip split and heterogeneous integration (driven by cost and yield), (c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, (d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, and (e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate will be investigated. Items (c), (d), and (e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.
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来源期刊
Journal of Electronic Packaging
Journal of Electronic Packaging 工程技术-工程:电子与电气
CiteScore
4.90
自引率
6.20%
发文量
44
审稿时长
3 months
期刊介绍: The Journal of Electronic Packaging publishes papers that use experimental and theoretical (analytical and computer-aided) methods, approaches, and techniques to address and solve various mechanical, materials, and reliability problems encountered in the analysis, design, manufacturing, testing, and operation of electronic and photonics components, devices, and systems. Scope: Microsystems packaging; Systems integration; Flexible electronics; Materials with nano structures and in general small scale systems.
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