基于3:2压缩机的节能倍增器设计

I. Hussain, S. Chaudhury
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引用次数: 0

摘要

乘法器电路是许多纳米电子、控制和自动化应用中最重要的功能块之一。在这项工作中,报道了一种基于3:2压缩机的节能乘法器。乘法器分为三个不同的部分设计。在第一部分中,使用了偏积(PP)生成器。在第二部分中,部分产品被减少,这被称为PPP(部分产品处理)。而在第三步骤中进行最后的添加。PP是通过使用AND门产生的。PPP分两个阶段设计。在第一阶段中,使用Wallace树对数来减少PP。而在第二阶段,通过使用节能的半加法器和3:2压缩器来减少PP。最后,在第三步中,使用进位保存加法器计算了最终加法。对所设计的乘法器进行了性能分析,并与其他乘法器电路进行了比较。在1.2 V到0.6 V的电源变化范围内,乘法器的性能提高了20.55%-46%。所有模拟和分析都是使用Synopsys EDA工具进行的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of energy-efficient multiplier based on 3:2 compressor
A multiplier circuit is one of the most important functional blocks of many nano-electronic, control and automation applications. In this work, an energy-efficient multiplier is reported based on a 3:2 compressor. The multiplier has been designed in three different parts. In the first part, a partial product (PP) generator is used. In the second part, the partial products are reduced which is termed as PPP (partial product processing). Whereas in the third step final addition is performed. PPs are produced by using AND gates. The PPP is designed in two-phase. In the first phase, the Wallace tree logarithm has been used to reduce the PPs. Whereas, in the second phase the PPs are reduced by using energy-efficient half adder and 3:2 compressor. At last, in the third step, by using a carry-save adder final addition has been computed. The performance analysis of the designed multiplier is evaluated and compared with other multiplier circuits. The multiplier shows performance improvements by 20.55%-46% for the power supply variation from 1.2 V to 0.6 V. All the simulations and analyses have been carried out by using the Synopsys EDA tool.
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CiteScore
6.80
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