{"title":"用于高性能OTDR应用的79 dBΩ 1.2 GHz低噪声单端CMOS跨阻放大器","authors":"A. Romanova, V. Barzdenas","doi":"10.2478/ecce-2019-0015","DOIUrl":null,"url":null,"abstract":"Abstract The work reports on the design and performance of a low-noise low-cost CMOS transimpedance amplifier (TIA). The proposed circuit shall be employed in optical time-domain reflectometers and is implemented using an affordable 0.18 µm 1.8 V CMOS process. The approach preserves the benefits of a classical feedback structure while addressing the noise problem of conventional feed-forward and resistive feedback architectures via the usage of noise-efficient capacitive feedback. Circuit-level modifications are proposed to mitigate the voltage headroom and DC current issues. The suggested design achieves a total gain of 82 dBΩ (79 dBΩ after the output buffer) within the bandwidth of 1.2 GHz while operating with a total input capacitance of 0.7 pF. The simulated average input-referred noise current density is below 1.8 pA/sqrt(Hz) with the power consumption of the complete amplifier including the output buffer being 21 mW.","PeriodicalId":42365,"journal":{"name":"Electrical Control and Communication Engineering","volume":"15 1","pages":"113 - 118"},"PeriodicalIF":0.5000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 79 dBΩ 1.2 GHz Low-Noise Single-Ended CMOS Transimpedance Amplifier for High-Performance OTDR Applications\",\"authors\":\"A. Romanova, V. Barzdenas\",\"doi\":\"10.2478/ecce-2019-0015\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Abstract The work reports on the design and performance of a low-noise low-cost CMOS transimpedance amplifier (TIA). The proposed circuit shall be employed in optical time-domain reflectometers and is implemented using an affordable 0.18 µm 1.8 V CMOS process. The approach preserves the benefits of a classical feedback structure while addressing the noise problem of conventional feed-forward and resistive feedback architectures via the usage of noise-efficient capacitive feedback. Circuit-level modifications are proposed to mitigate the voltage headroom and DC current issues. The suggested design achieves a total gain of 82 dBΩ (79 dBΩ after the output buffer) within the bandwidth of 1.2 GHz while operating with a total input capacitance of 0.7 pF. The simulated average input-referred noise current density is below 1.8 pA/sqrt(Hz) with the power consumption of the complete amplifier including the output buffer being 21 mW.\",\"PeriodicalId\":42365,\"journal\":{\"name\":\"Electrical Control and Communication Engineering\",\"volume\":\"15 1\",\"pages\":\"113 - 118\"},\"PeriodicalIF\":0.5000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electrical Control and Communication Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.2478/ecce-2019-0015\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electrical Control and Communication Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2478/ecce-2019-0015","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 1
摘要
本文报道了一种低噪声、低成本的CMOS跨阻放大器(TIA)的设计与性能。所提出的电路将用于光学时域反射计,并使用价格合理的0.18µm 1.8 V CMOS工艺实现。该方法保留了经典反馈结构的优点,同时通过使用低噪声的电容反馈解决了传统前馈和电阻反馈结构的噪声问题。提出了电路级修改以减轻电压净空和直流电流问题。该设计在1.2 GHz带宽范围内实现了82 dBΩ(含输出缓冲器后为79 dBΩ)的总增益,而总输入电容为0.7 pF,模拟的平均输入参考噪声电流密度低于1.8 pA/sqrt(Hz),整个放大器包括输出缓冲器的功耗为21 mW。
A 79 dBΩ 1.2 GHz Low-Noise Single-Ended CMOS Transimpedance Amplifier for High-Performance OTDR Applications
Abstract The work reports on the design and performance of a low-noise low-cost CMOS transimpedance amplifier (TIA). The proposed circuit shall be employed in optical time-domain reflectometers and is implemented using an affordable 0.18 µm 1.8 V CMOS process. The approach preserves the benefits of a classical feedback structure while addressing the noise problem of conventional feed-forward and resistive feedback architectures via the usage of noise-efficient capacitive feedback. Circuit-level modifications are proposed to mitigate the voltage headroom and DC current issues. The suggested design achieves a total gain of 82 dBΩ (79 dBΩ after the output buffer) within the bandwidth of 1.2 GHz while operating with a total input capacitance of 0.7 pF. The simulated average input-referred noise current density is below 1.8 pA/sqrt(Hz) with the power consumption of the complete amplifier including the output buffer being 21 mW.